The present disclosure relates to semiconductor memory devices, and more particularly, to flash memory devices including a program sequencer. The present disclosure also relates to memory systems incorporating this type of flash memory device, as well as related programming methods.
Generally, semiconductor memory devices may be divided into volatile memories such as Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), and nonvolatile memories such as Electrical Erasable Programmable Read Only Memory (EEPROM)—including flash memory, Ferroelectric Random Access Memory (FRAM), Phase-change Random Access Memory (PRAM), and Magneto-resistive Random Access Memory (MRAM). Of the many different types of semiconductor memory devices, flash memory devices exhibit a unique combination of high programming speed, low power consumption, dense memory cell integration, and nonvolatile data storage. As a result, flash memory devices have been widely adopted for use as a storage medium in all sorts of consumer electronics and digital data systems.
Contemporary flash memory devices are capable of storing a single data bit per memory cell in single-level memory cells (SLCs), and/or two or more data bits per memory cell in multi-level memory cells (MLCs). Thus, a SLC stores data binary having either an erase state or a programmed state according to corresponding threshold voltage distributions. A MLC stores multi-bit data having either an erase state or one of multiple programmed states according to corresponding threshold voltage distributions.
Stored data is read from a SLC or MLC during read (or verify) operations in accordance with respective threshold voltage distributions using one or more reference voltages that effectively discriminate between the threshold voltage distributions. The voltage separation between adjacent threshold voltage distributions is referred to as “read margin.”
Unfortunately, as the number of valid states in MLCs increases, the various read margins between adjacent threshold voltage distributions are reduced. Further challenging the proper execution of read (verify) operations (e.g., the maintenance of defined read margins) is the fact that threshold voltage distributions may change over time in response to a number of influences. For example, the execution of a programming operation, an erase operation and/or a read operation directed to a target memory cell may unintentionally change (e.g., shift, expand or reduce) the threshold voltage of an adjacent memory cell (i.e., a memory cell physically proximate the target memory cell in a memory cell array). In certain worse case scenarios, adjacent threshold voltage distributions intended to clearly indicate different erase/programming states may actually overlap making it impossible to discriminate one data state from the other. As a result, a read operation failure may arise. Other factors potentially changing the threshold voltage of memory cells in a memory cell array include; coupling noise effects, pass voltage disturbance effects, and programming voltage disturbance effects to name but a few examples.